1. Field of the Invention
The present invention relates to a display apparatus for characters, pictures and others and, more particularly, to a display apparatus capable of presenting a gray-scale expression based on a digital signal.
2. Description of the Background Art
Display apparatuses having liquid crystal elements or electroluminescence (EL) elements as display pixels have been employed as display panels of a personal computer, a television receiver, a portable telephone, a portable information terminal and others. Such display apparatuses have greater merits in respects of lower power consumption and smaller size and weight as compared with those of conventional types.
An pixel including a liquid crystal element or an EL element alters a display brightness thereof according to a level of an applied voltage (a voltage applied to an pixel will be also referred to as “display voltage”). Therefore, in such pixels, display voltages are set with a series of levels in a gradual manner so as to be adaptable for intermediate brightness values, thereby enabling gray-scale expression to be realized. In general, display voltages are set stepwise according to respective decode results of digital signals each of a plurality of bits for gray-scale.
Hence, a display apparatus capable of gray-scale expression requires a decode circuit for decoding a digital signal to recognize a designated gray level. Generally, since in the decode circuit, many transistor switches are necessary for decoding, there has been a task to reduce a scale of the circuit.
In order to solve such a problem, disclosed in Japanese Patent Laying-Open No. 2001-34234 is a configuration of a decode circuit referred to as a so-called “tournament scheme”.
In this scheme, disclosed are a configuration of a decode circuit in which n-MOS (Metal Oxide Semiconductor) transistors of N in number are connected serially between each of nodes on which 2 to the nth power levels (hereinafter, referred to as 2^N”) of gray-scale voltages are generated, respectively, and the corresponding one of nodes on which display voltages are generated, respectively, when 2^N gray levels are displayed according to digital signals each of N bits (N is an integer of 2 or more), and a configuration of a decode circuit in which reduction is made in the number of n-MOS transistors connected serially in each transmission path of gray-scale voltages.
In the configuration of a decode circuit shown in FIG. 8 of the above publication, however, a decode circuit area can be down-sized, whereas a necessity arises for a voltage drop caused by a threshold voltage of an n-MOS transistor to be compensated. Hence, a gate voltage of each of n-MOS transistors included in the decode circuit requires to be set higher than a gray-scale voltage to be transmitted by at least the threshold of an n-MOS transistor.
For this reason, an amplitude of a gate voltage is larger, which also makes a noise amplitude larger that can be transmitted through a parasitic capacitance created between a gate electrode of an n-MOS transistor and a source electrode or a drain voltage thereof, thereby causing a problem of an enhanced influence on a display voltage applied to a pixel.
In a decode circuit shown in FIG. 9 of the above publication, reduction is made in the number of n-MOS transistors included in each transmission path of gray-scale voltages, thereby enabling a drop of a gray-scale voltage to be suppressed. On the other side, since increase is required in the number of transistors required in the decode circuit as a whole, a problem arises in respect of down-sizing and a production yield of the circuit.